Firmware-over-the-air (FOTA), and other firmware update methods, can be a key requirement for computing systems. FOTA updates typically need to be transparent, i.e., old and new FW image are switched instantaneously. Conventionally, systems that need to update firmware employ two or more separate flash memory devices that are mapped (e.g., via use of base registers) into different ranges of a processor address space. A base address of each different address range controls a single chip select, which selects the desired flash memory device. Thus, the instantaneous switch occurs by swapping the base addresses stored in the base address registers.
FIG. 16A shows a conventional system 1691 that includes FOTA updating. System 1691 can include a microcontroller (MCU) 1693 and multiple flash memory devices 1695-0 to -2. Storage locations within flash memory devices (1695-0 to -2) can be mapped to a system address space 1697. Flash memory device 0 1695-0 can correspond to a base address 0x000 and can store an old firmware image 1607-0 (i.e., an outdated version that has since been replaced). Flash memory device 1 1695-1 can correspond to a base address 0x100 and can store a current firmware image 1697-1 (i.e., a version that is currently accessed by the system). Flash memory device 2 1695-2 can correspond to a base address 0x200 and can store a new firmware image 1697-2 (i.e., a version intended to update current image 1697-1).
MCU 1693 can update the firmware image using addressing mechanisms inside the MCU 1693. MCU 1693 can have base address registers 1699 that store base addresses corresponding to firmware images. Base address registers 1699 are used to generate chip select signal CS0-CS2 for flash memory devices 1695-0 to -2, respectively. Base address register “ba_new_image” can store the base physical address of a new firmware image (0x200 before an update). Base address register “ba_cur_image” can store the base physical address of a current firmware image (0x100 before an update). Base address register “ba_old_image” can store the base physical address of an old firmware image (0x000 before an update).
System 1691 can update from a current image (e.g., 1697-1) to the new image (e.g., 1697-2) by exchanging values in the base address registers 1699. In particular, the value in base address register ba_cur_image can be switched from “cfg_cur” to “cfg_new”. Following such an operation, when a system 1691 goes to read the firmware, the addressing mechanisms internal to MCU 1693 will access a base address that generates chip select signal CS2 (instead of CS1, as was done prior to the update operation).
FIG. 16B is a block diagram of a conventional system 1691 showing how chip selects are used. MCU 1693 dedicates an output (e.g., I/O) as a chip select (CS1, CS2) for each flash memory device 1695-0/1. As understood from above, such chip selects (CS1, CS2) can be activated according to values in base addresses registers. One flash memory device (e.g., 1695-0) can store a firmware image that is currently in use, while the other flash memory device (e.g., 1695-1) can store a firmware image that is not currently in use (i.e., an old firmware image, or a new firmware image to be put in use by switching base address register values).
A drawback to conventional FOTA approaches can be cost and limitations in performance. If a typical controller (e.g., MCU) is used that dedicates an I/O as a chip select for each flash memory device (i.e., each firmware image), the controller may not have a free I/O for other needed devices, such as dynamic RAM (DRAM) or static RAM (SRAM). As a result, a controller with additional I/Os may have to be used, which can increase costs of system. While conventional systems can connect multiple flash memory devices to the same bus, with each added flash memory device, capacitive loading on the bus can increase. Thus, the larger the number of flash memory devices on the bus, the slower the bus will perform. As but one example, for an Octal SPI bus, adding two flash memory devices can drop maximum bus speed from 200 MHz to 133-166 MHz, as compared the same bus with only one flash memory device.